A phase of the output signal may be related to a phase of an input reference signal. A PLL circuit may comprise a phase frequency detector (PFD), a charge pump (CP), a loop filter, and a voltage-controlled oscillator (VCO). In use, the PFD may compare the phase of the input reference signal with the phase of a signal derived from an output of the VCO. The PLL may adjust the frequency of its oscillator output to keep the two phases matched. To form a PLL circuit, the PFD may generate an output representing an error between the input reference and the oscillator. The error signal may be fed to the loop filter, which may integrate the signal to smooth it. Then, the smoothed signal may be fed into the VCO, which may generate an output signal with a frequency that is proportional to the smoothed signal (e.g., a tuning voltage signal). The VCO output may also be fed back to the PFD to complete the loop structure of the PLL.
Frequency is a time derivative of phase. Keeping the input and output phase in a locked state may imply keeping the input and output frequencies in a locked state. Consequently, a phase-locked loop may track an input frequency, or it may generate a frequency that is a multiple of the input frequency.
A common application of a PLL is in anlog to digital converter (ADC) applications. Current ADC structures require clocking purity of tenths of femto seconds. Clocking purity can be adversely affected by a number of factors, with three main clocking jitter contributors being charge pump jitter, reference clock jitter and VCO jitter. Accordingly, controlling charge pump noise can be an important aspect of PLL noise reduction. PLL designs that omit a charge pump are possible, including for example designs that use time-to-digital (TDC) circuits and digital filters in the place of charge pumps. However, such charge pump-less circuits tend to occupy the low end of the PLL performance spectrum and require high precision and high current TDC circuits to improve performance.
Accordingly, an improved charge pump configuration for use in a PLL is desired.